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PulseGuard ? Suppressors
Surface Mount Polymeric ESD Suppressors
Characterization Methods for ESD Suppressors
Two of the most common methods used in industry for
characterizing the performance of ESD suppressors are
ESD transient testing, per IEC 61000-4-2 ESD waveform,
Figure 1
100%
90%
quali?cation of ESD suppressor performance, these
two methods have become the de-facto standard for
determining device trigger and clamp speci?cations. It
is common to see trigger values to be based on the TLP
method and clamping values based on the ESD transient
method. Low voltage TLP obtained trigger values most
closely resemble device DC turn-on .Since the two test
I 30
I 60
10%
correlate suppressor response between the two test
methods, trigger and clamp values should be speci?ed for
each method.
ESD transient testing, which is based on the IEC 61000-4-2
standard waveform, consists of subjecting a ESD
tr = 0.7 to 1.0ns
Figure 2
30n
60n
suppressor to an subnanosecond risetime 8Kv transient
generated by a commercial ESD simulator and recording
trigger and clamp voltage levels. Clamp voltage level is
obtained at 25ns. The basic ESD simulator circuit consists
ESD Simulator
1
2
330
Scope Probe
9 5 0
30db Attenuator
46.93
46.93
50 Ohm
Scope Input
+
8000
1 5 0pf
DUT
3.16 5
5 0
4 GHz oscilloscope(50 ohm input) with 20X resistive divider
probes and a 30dB attenuator. Figures 1 and 2 show IEC
current waveform and test setup.
TLP testing consists of subjecting a ESD suppressor
to a 50 ohm transmission line discharge pulse with a
subnanosecond risetime and a pulse width of 65ns. Trigger
-
Figure 3
600
values are obtained by varying the TLP voltage until a
5 00
are captured using a 4 GHz oscilloscope(50 ohm input)
with 20X resistive divider probes and a 30dB attenuator.
Figures 3 and 4 show a typical TLP voltage waveform and
test setup.
for obtaining trigger and clamp voltage levels. Trigger and
400
300
200
100
clamp values will vary from one test setup to another.
Due to the subnanosecond risetime of ESD and TLP
0
0
20
40
60
80
waveforms, any parasitic inductance and capacitance in
due to inductance and capacitance need to be subtracted
Figure 4
Time in nanoseconds
from the ?nal measurement. It is important to remember
that the test system will introduce a load across the
TLP
1
2
Scope Probe
30db Attenuator
50 Ohm
Scope Input
ESD suppressor under test and this will also affect
9 5 0
46.93
46.93
and probes(>1Ghz) need to be used for obtaining best
+
5 00
DUT
3.16 5
5 0
-
at least 20X in order to obtain high input impedance for
measurements.
PGB2 Series
Speci?cations are subject to change without notice.
5
Revised: March 8, 2011
www.littelfuse.com
?2011 Littelfuse
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